1. Field of the Invention
This invention relates generally to memory systems, and more particularly to system and method for reducing electrical loading in a DIMM-based memory system.
2. Description of the Related Art
Traditional computer systems, such as servers, workstations, desktops and laptops, all use pluggable memory which can be inserted into slots on the computer's motherboard as needed. The most common form of pluggable memory is the dual-inline memory module (DIMM). Historically, DIMMs contain multiple RAM chips—typically DRAM—each of which has a data bus width of 4 or 8 bits. A basic ‘unbuffered’ DIMM 10 is shown in FIG. 1. Typically, eight or nine 8-bit DRAM chips 12 (or twice as many 4-bit DRAM chips) are arranged in parallel to provide the DIMM with a total data bus width of 64 or 72 bits; the data bus, typically referred to as the ‘DQ’ bus, is connected to a host controller 14. Each arrangement of 64 or 72 data bits using DRAM chips in parallel is termed a ‘rank’ 16. The DRAM chips within a DIMM may be connected in a parallel arrangement—which may include stacking of DRAM chips within the same package—to provide additional ranks (18).
A command/address (CA) bus (not shown) also runs between the host controller and the DIMMs; the CA and DQ busses together form a ‘system’ bus. With a basic unbuffered DIMM, the CA bus is connected to every DRAM on the DIMM. As a result, there is a high electrical load on the CA bus, given by the product of the number of DRAMs times the number of ranks. For the DQ bus, the number of electrical loads is equal to the number of ranks.
For higher performance, ‘registered’ DIMMs (RDIMMs) may be used. Here, a special buffer device is used to drive the CA bus to the DRAMs. When so arranged, the number of electrical loads on the system bus will be 1 CA load for each DIMM and 1 DQ load for each rank.
A newly emerging technology is employed in a ‘load reduction’ DIMM (LR-DIMM), an example of which is illustrated in FIG. 2. An LR-DIMM 20 uses a logic device 22 to buffer the DQ signals between the DIMM ranks and the system channel, as well as provide the function of the buffer device of an RDIMM. Logic device 22 may be, for example, a single device such as the iMB (isolating Memory Buffer) from Inphi Corporation. When so arranged, there is only one electrical load on the DQ bus, and one load on the CA bus.
As noted above, a DIMM may contain multiple ranks, and multiple DIMMs may be fitted into a computer system. However, the ranks are fixed in position which gives rise to some non-optimal system constraints:                each system channel connected to a group of n DIMMs will have n loads on the interconnecting channel. This may limit the maximum operating frequency of a given DIMM configuration due to signal integrity issues with either the CA bus, the DQ bus, or both.        when a rank of memory is accessed, all of the power and resulting heat is concentrated on a single DIMM, so each DIMM slot has to be designed to tolerate the instantaneous maximum power consumption of any DIMM. This means that external power delivery components and connections have to be able to handle the peak power of any DIMM that can be installed into the system; conversely, DIMMs that have a peak power above what the system can handle will necessarily be excluded.        if a single DIMM is continually accessed, then the power and resulting heat is continuously concentrated; as such, each DIMM slot has to be designed to deal with the maximum heat dissipated by any DIMM in every DIMM slot.        systems employ ‘DQS strobe’ signals, which are associated with each nibble or byte on the DQ bus. To properly control contention on the DQ bus, these signals must meet various requirements. For example, gaps are needed between DQS strobe signals, due, for example, to read and write runarounds which could be different from rank to rank on the same DIMM, or from DIMM to DIMM. Different gaps might also be needed for read to read and write to write, both for rank to rank on the same DIMM, as well as for DIMM to DIMM. The gaps could also be different depending on the DIMM configuration of the channel or system.        